1. Field of the Invention
This invention relates to a method for driving a plasma display panel.
2. Description of the Related Art
As a thin display device, at present, there has been placed in the market an AC discharge type plasma display panel. The plasma display panel emits light by utilizing the discharge phenomenon and assumes only two states, i.e., a light emitting state corresponding to a maximum brightness level and a non-light emitting state corresponding to a minimum brightness level. In order to obtain a display brightness of a half tone corresponding to a video signal, therefore, a gradation drive is effected for the plasma display panel based upon a sub-field method. In the sub-field method, a display period of a field is divided into N sub-fields to meet the bit digits of pixel data of N bits corresponding to the video signal. A number of times of emitting light (light emitting period) corresponding to the weighting of each bit digit of pixel data is assigned to each of the N sub-fields. The discharge cells are selected to emit light in response to the pixel data bit in each sub-field.
FIG. 1 is a diagram schematically illustrating the construction of a plasma display apparatus for gradation-driving the plasma display panel relying upon the sub-field method.
In FIG. 1, the plasma display panel PDP 10 includes column electrodes D1 to Dm of a number of m, row electrodes X1 to Xn of a number of n and row electrodes Y1 to Yn of a number of n arranged to intersect the column electrodes. Each pair of row electrodes X and Y produce a display line on the PDP 10. The column electrodes D and the row electrodes X and Y are covered with a dielectric layer for discharge space. A discharge cell that works as a pixel is formed at every portion where a pair of row electrodes intersect a column electrode.
A drive unit 100 gradation-drives the PDP 10 in compliance with a light emission drive format shown in FIG. 2.
In the drive according to the light emission drive format shown in FIG. 2, a display period of a field is divided into six sub-fields SF1 to SF6. A simultaneous resetting step Rc, a pixel data writing step Wc, a light emission-sustaining step Ic and an erasing step E are executed in each sub-field.
FIG. 3 is a timing diagram (in a sub-field) for applying drive pulses to the column electrodes and to the pairs of row electrodes in the PDP 10 by the drive unit 100 to execute the above steps.
In the simultaneous resetting step Rc, first, the drive unit 100 applies a reset pulse RPX of the negative polarity and a reset pulse RPY of the positive polarity to the row electrodes X1 to Xn and Y1 to Yn, simultaneously. In response to the application of these reset pulses RPX and RPY, the discharge cells in the PDP 10 all undergo a reset discharge. At this moment, a wall charge of a predetermined quantity is formed uniformly in each discharge cell. Accordingly, every discharge cell is once initially set to be a xe2x80x9clight emitting cellxe2x80x9d.
Next, in the pixel data writing step Wc, the drive unit 100, first, converts the video signal that is received into pixel data of 6 bits for each of the pixels. A first bit of the pixel data is used in the pixel data writing step Wc in a sub-field SF1, a second bit is used in the pixel data writing step Wc in a sub-field SF2, a third bit is used in the pixel data writing step Wc in a sub-field SF3, a fourth bit is used in the pixel data writing step Wc in a sub-field SF4, a fifth bit is used in the pixel data writing step Wc in a sub-field SF5 and a sixth bit is used in the pixel data writing step Wc in a sub-field SF6. The drive unit 100 generates a pixel data pulse corresponding to the logic level of each bit in the pixel data, and applies it to the column electrodes D1 to Dm. For example, in the pixel data writing step Wc in the sub-field SF1, the drive unit 100 gives attention to a first bit only of the pixel data, and generates a pixel data pulse of a high voltage when the first bit has a logic level xe2x80x9c1xe2x80x9d and generates a pixel data pulse of a low voltage (0 bolt) when the first bit has a logic level xe2x80x9c0xe2x80x9d. The drive unit 100 applies pixel data pulse groups DP1, DP2, DP3, . . . , DPn to the column electrodes D1 to Dm successively as shown in FIG. 3, each of the pixel data pulse groups DP1, DP2, DP3, . . . , DPn consisting of m pixel data pulses and corresponding to each of the first to n-th display lines in the PDP 10. The drive unit 100 further applies the scanning pulses SP of the negative polarity shown in FIG. 3 successively to the row electrodes Y1 to Yn at the same timings as the timings of applying the pixel data pulse groups DP. Here, a discharge (selectively erasing discharge) takes place in only the discharge cells at portions where the xe2x80x9crowsxe2x80x9d to which the scanning pulse SP is applied are intersecting the xe2x80x9ccolumnsxe2x80x9d to which the pixel data pulse of a high voltage is applied, and the wall charge remaining in the discharge cells is erased. Due to the selectively erasing discharge, the discharge cells initialized to the state of xe2x80x9clight emitting cellsxe2x80x9d in the simultaneously resetting step Rc turn into the xe2x80x9cnon-light emitting cellsxe2x80x9d. The selectively erasing discharge does not occur in the discharge cells to which the pixel data pulse of a low voltage is applied simultaneously with the application of the scanning pulse SP. Therefore, the discharge cells are maintained in a state of xe2x80x9clight emitting cellsxe2x80x9d.
Next, in the light emission-sustaining step Ic, the drive unit 100 alternately applies the sustain pulses IPX and IPY shown in FIG. 3 to the row electrodes X1 to Xn and Y1 to Yn. Here, the number of times (period) of applying the sustain pulses IPX and IPY in each light emission-sustaining step Ic, is set depending upon the weighting of each of the sub-fields. That is, as shown in FIG. 2, the sustain pulses IPX and IPY are repetitively applied numbers of times (periods) for example:
SF1 : 1
SF2 : 2
SF3 : 4
SF4 : 8
SF5 : 16
SF6 : 32
After the pixel data writing step Wc has been finished, only those discharge cells in which the wall charge is remaining undergo the sustain discharge, i.e., only those discharge cells in a state of xe2x80x9clight emitting cellsxe2x80x9d undergo the sustain discharge every time when the sustain pulses IPX and IPY are applied. Therefore, the discharge cells in the state of xe2x80x9clight emitting cellsxe2x80x9d, emit light accompanying the discharge the above-mentioned numbers of times (periods). In the discharge cells in the state of xe2x80x9cnon-light emitting cellsxe2x80x9d, on the other hand, the above-mentioned discharge does not occur even when, for example, a sustain pulse is applied, and the discharge cells stay in the non-light emitting state.
Next, in the erasing step E, the drive unit 100 applies the erasing pulse EP shown in FIG. 3 to the row electrodes Y1 to Yn, whereby the discharge cells all undergo an erase discharge simultaneously to thereby erase the wall charge remaining in the discharge cells.
In the above gradation drive, when a video signal corresponding to, for example, a brightness level xe2x80x9c18xe2x80x9d (corresponding to pixel data xe2x80x9c101101xe2x80x9d) is fed, light is emitted in the light emission-sustaining step IC in the sub-fields SF2 and SF5 among the sub-fields SF1 to SF6. Therefore, light is emitted a total of 18 times in a field, i.e., 2 times in SF2 and 16 times in SF5, and a half brightness corresponding to the brightness xe2x80x9c18xe2x80x9d is seen. According to the gradation drive using the above six sub-fields SF1 to SF6, therefore, a half bright display of 64 gradations can be realized in a brightness range of from a brightness level xe2x80x9c0xe2x80x9d to brightness level xe2x80x9c63xe2x80x9d.
According to the sub-field method, the number of gradations increase with an increase in the number of the sub-fields, and a picture is displayed in a higher quality. Further, the display is obtained in a higher brightness if the number of times of emitting light is increased in the light emission-sustaining step Ic in the sub-fields.
However, since the display period of a field has been specified, limitation is imposed on the number of the sub-fields that are divided and on the number of times of emitting light in the light emission-sustaining step Ic in each sub-field. With the above method, therefore, it is therefore difficult to realize a display quality maintaining a high degree of brightness and a high degree of gradation.
In gradation-driving the plasma display panel relying upon the sub-field method, therefore, it is an object of this invention to provide a driving method capable of realizing a favorable display quality.
According to the invention, there is provide a method for driving a plasma display panel having discharge cells each corresponding to one pixel formed at each of intersecting points between a plurality of row electrodes corresponding to display lines and a plurality of column electrodes intersecting said row electrodes, in response to a video signal, at each of successively appearing sub-fields forming each of the fields of said video signal, which comprises: in each of said sub-fields, executing a pixel data writing step for setting said discharge cell to one of a light emitting state and a non-light emitting state in accordance with pixel data corresponding to the video signal; and a light emission sustaining step for causing only said discharge cell in said light emitting state to emit light by only a number of times assigned in relation to the weighting of each of said sub-fields, wherein in the pixel data writing step in a sub-field of a small weighting, one of said light emitting state and said non-light emitting state is selected every a plurality of said display lines which are simultaneously scanned, in the pixel data writing step in other sub-fields, one of said light emitting state and said non-light emitting state is selected at a display line.